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AT45DB642
RESET: A low state on the reset pin (RESET) will terminate the operation in progress and
reset the internal state machine to an idle state. The device will remain in the reset condition
as long as a low level is present on the RESET pin. Normal operation can resume once the
RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. The RESET pin is also internally pulled high; there-
fore, in low pin count applications, connection of the RESET pin is not necessary if this pin and
feature will not be utilized. However, it is recommended that the RESET pin be driven high
externally whenever possible.
READY/BUSY: This open drain output pin will be driven low when the device is busy in an
internally self-timed operation. This pin, which is normally in a high state (through an external
pull-up resistor), will be pulled low during programming/erase operations, compare operations,
and page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
PARALLEL PORT SUPPLY VOLTAGE (VCCP AND GNDP): The VCCP and GNDP pins are
used to supply power for the parallel input/output pins (I/O7-I/O0). The VCCP and GNDP pins
need to be used if the parallel port is to be utilized; however, these pins should be treated as
“ don ’ t connects ” if the SER/PAR pin is not connected or if the SER/PAR pin is always driven
high externally.
Power-on/Reset
State
System
Considerations
When power is first applied to the device, or when recovering from a reset condition, the
device will default to SPI Mode 3 or Inactive Clock Polarity High. In addition, the output pins
(SO or I/O7 - I/O0) will be in a high impedance state, and a high-to-low transition on the CS pin
will be required to start a valid instruction. The SPI mode or the clock polarity mode will be
automatically selected on every falling edge of CS by sampling the inactive Clock State.
The SPI interface is controlled by the serial clock SCK, serial input SI and chip select CS pins.
The sequential 8-bit parallel interface is controlled by the clock CLK, 8 I/Os and chip select CS
pins. These signals must rise and fall monotonically and be free from noise. Excessive noise
or ringing on these pins can be misinterpreted as multiple edges and cause improper opera-
tion of the device. The PC board traces must be kept to a minimum distance or appropriately
terminated to ensure proper operation. If necessary, decoupling capacitors can be added on
these pins to provide filtering against noise glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A
key element of any voltage regulation scheme is its current sourcing capability. Like all Flash
memories, the peak current for DataFlash occur during the programming and erase operation.
The regulator needs to supply this peak current requirement. An under specified regulator can
cause current starvation. Besides increasing system noise, current starvation during program-
ming or erase can lead to improper operation and possible data corruption.
11
1638F – DFLSH – 09/02
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